# EHIP RX Block Lock is high at time 467376591 # EHIP RX reset ack is 0 at time 463283667 # EHIP RX reset out is 0 at time 463088000 # EHIP TX reset ack is 0 at time 462643731 # EHIP TX reset out is 0 at time 413160000
# EHIP PLD Ready out is 1 at time 410776000 # RX transfer ready is 1 at time 410719813 # TX transfer ready is 1 at time 399169435 The following sample output illustrates a successful simulation test run for a 100GE, MAC+PCS with optional RS-FEC IP core variation. The client logic then checks the number of packets received and verify that the data matches with the transmitted packets.
#Lrtimelapse 3.2.1 for mac series#
The client logic receives the same series of packets through RX MAC interface.Once alignment is complete, client logic transmits a series of packets to the IP core.
The successful test run displays output confirming the following behavior: The simulation model with the testbench implements an alignment marker interval of 512 words. The standard specifies an alignment marker interval of 16,384 words in each virtual lane. To speed up simulation, the IP core simulation model sends alignment marker tags at shorter intervals than required by the IEEE Ethernet standard. The testbench sends traffic through the IP core, exercising the transmit side and receive side of the IP core. Note: If Enable asynchronous adapter clocks is enabled, the o_clk_div66 feeds the i_clk_tx and i_clk_rx clocks.
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